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Our paper is accepted in HPCA 2016

Our paper titled ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality has been accepted in International Symposium on High Performance Computer Architecture (HPCA) 2016, Barcelona, Spain. Paper: http://www.kasirgalabs.com/wp-content/uploads/2016/04/chargecache_low-latency-dram_hpca16.pdf Slides (pdf): http://www.kasirgalabs.com/wp-content/uploads/2016/04/chargecache_low-latency-dram_hhassan_hpca16-talk.pdf Slides (pptx): http://www.kasirgalabs.com/wp-content/uploads/2016/04/chargecache_low-latency-dram_hhassan_hpca16-talk.pptx Abstract: DRAM latency continues to be a critical bottleneck for system performance. In this work, we develop a low-cost mechanism, called Charge Cache, that enables faster access to recently-accessed rows in DRAM, with no modifications to DRAM chips. Our mechanism is based on the key observation that a recently-accessed row has more charge and thus the following access to the same row can be performed faster. To exploit this observation, we propose to track the addresses of recently-accessed rows in a table in the memory controller. If a later DRAM request hits in that table, the memory controller uses lower timing parameters, leading to reduced DRAM latency. Row addresses are removed from the table after a specified duration to ensure rows that have leaked too much charge are not accessed with lower latency. We evaluate ChargeCache on a wide variety of workloads and show that it provides significant performance and energy benefits for both single-core and multi-core...

Onur Mutlu visited our laboratory

Assoc. Prof. Onur Mutlu from Carnegie Mellon University visited our laboratory and gave a talk about Rethinking Memory System Design for Data-Intensive Computing. Abstract: The memory system is a fundamental performance and energy bottleneck in almost all computing systems. Recent system design, application, and technology trends that require more capacity, bandwidth, efficiency, and predictability out of the memory system make it an even more important system bottleneck. At the same time, DRAM and flash technologies are experiencing difficult technology scaling challenges that make the maintenance and enhancement of their capacity, energy-efficiency, and reliability significantly more costly with conventional techniques. In this talk, we examine some promising research and design directions to overcome challenges posed by memory scaling. Specifically, we discuss three key solution directions: 1) enabling new memory architectures, functions, interfaces, and better integration of the memory and the rest of the system, 2) designing a memory system that intelligently employs multiple memory technologies and coordinates memory and storage management using non-volatile memory technologies, 3) providing predictable performance and QoS to applications sharing the memory/storage system. If time permits, we might also briefly touch upon our ongoing related work in combating scaling challenges of NAND flash memory. An accompanying paper can be found here: http://users.ece.cmu.edu/~omutlu/pub/memory-systems-research_superfri14.pdf Bio: Onur Mutlu is the Strecker Early Career Professor at Carnegie Mellon University. His broader research interests are in computer architecture, systems, and bioinformatics. He is especially interested in interactions across domains, between applications, system software, compilers, and microarchitecture, with a major current focus on memory systems. He obtained his PhD and MS in ECE from the University of Texas at Austin and BS...

Volkan Keles is intern at Apple

Volkan Keles is intern at Apple
Between April 2015 and August 2015, he will intern at Apple. There, he will work with Development Technologies team.