Erhan Baturay Onural will work on his research at Barcelona Supercomputing Center as a coop-education student. We wish him success in his research.
Mert Atamaner will work on his research at ETH Zürich SAFARI Research Group for the next year as a coop-education student. We wish him success in his research.
Hasan Hassan has left Kasirga to pursue a Phd at ETH Zürich. We wish him all success in his future endeavor.
Our paper titled ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality has been accepted in International Symposium on High Performance Computer Architecture (HPCA) 2016, Barcelona, Spain. Paper: http://www.kasirgalabs.com/wp-content/uploads/2016/04/chargecache_low-latency-dram_hpca16.pdf Slides (pdf): http://www.kasirgalabs.com/wp-content/uploads/2016/04/chargecache_low-latency-dram_hhassan_hpca16-talk.pdf Slides (pptx): http://www.kasirgalabs.com/wp-content/uploads/2016/04/chargecache_low-latency-dram_hhassan_hpca16-talk.pptx Abstract: DRAM latency continues to be a critical bottleneck for system performance. In this work, we develop a low-cost mechanism, called Charge Cache, that enables faster access to recently-accessed rows in DRAM, with no modifications to DRAM chips. Our mechanism is based on the key observation that a recently-accessed row has more charge and thus the following access to the same row can be performed faster. To exploit this observation, we propose to track the addresses of recently-accessed rows in a table in the memory controller. If a later DRAM request hits in that table, the memory controller uses lower timing parameters, leading to reduced DRAM latency. Row addresses are removed from the table after a specified duration to ensure rows that have leaked too much charge are not accessed with lower latency. We evaluate ChargeCache on a wide variety of workloads and show that it provides significant performance and energy benefits for both single-core and multi-core...